The present invention relates to the field of integrated circuits and integrated circuit manufacturing, and more particularly, to making interconnection structures with enhanced electromigration resistance, and while not significantly increasing the resistivity of the metal.
A metal interconnect system in wide use in the late 1990""s included an Al+Cu alloy interconnect line clad on each side with a barrier metal, and combined with planarized tungsten plugs for vias. A via is the structure that provides the electrical connection from one vertical level of interconnects to the next. The system saw wide acceptance in the industry, especially for high performance logic applications, such as microprocessor chips. The system was perceived as satisfactory, except that a severe degradation in electromigration resistance was noted on test patterns with multiple levels of interconnects and tungsten plug vias, versus test patterns using one interconnect level and no vias.
As much as a 100 times reduction in median-time-to-failure (T50) values, or more, were noted. One technical paper covering this phenomenon in detail is by R. G. Filippi et al., entitled, xe2x80x9cThe Effect of Copper Concentration on the Electromigration of Layered Aluminum-Copper (Tixe2x80x94AlCuxe2x80x94Ti) Metallurgy With Tungsten Diffusion Barriers.xe2x80x9d The paper appears in the 1992 VMIC Conference Proceedings, on page 359. The researchers showed that the copper doping is swept away from the tungsten in the direction of current flow. The aluminum, then depleted of its copper, electromigrates rapidly and voids appear at or near the W/Al interface. Increasing the concentration of copper helps to a limited extent, but degrades the resistivity. Stripes with a close by xe2x80x9creservoirxe2x80x9d of copper also showed improvement, but none of these measures completely solved the problem. In general, the phenomenon may be referred to as a flux divergence at a dissimilar material interface.
A similar phenomenon has been noted in a copper system with tungsten plugs. This was reported, for example, by Kazuhide Abe, et al., and coworkers in a paper entitled, xe2x80x9cCu Damascene Interconnects with Crystallographic Texture Control and Its Electromigration Performance,xe2x80x9d and appears in the IEEE 1998 Reliability Physics Symposium Proceedings on page 342.
The widely-accepted dual Damascene copper system does not use tungsten plugs between interconnect levels, but does employ a barrier metal. This barrier layer lies, in general, between the upper surface of a copper interconnect and the bottom of an overlying copper via. Thus, some flux divergence may occur at this interface at high current density. The location of the copper metal depletion depends on the direction of current flow. For example, if the current flows up into overlying metal, this is the area of voiding and damage.
In view of the foregoing background, it is therefore an object of the invention to provide a integrated circuit processing method which eliminates or significantly diminishes the flux divergence phenomenon such that little degradation of electromigration resistance occurs at the via structures relative to other regions in the interconnect system.
Another object of the invention is to provide a thin, hardened alloy skin on selected copper surfaces to increase electromigration resistance and/or provide for passivation.
These and other objects, features and advantages in accordance with the present invention are provided by a method for making an integrated circuit device comprising forming at least one interconnect structure adjacent a semiconductor substrate and comprising a copper portion and at least one barrier layer adjacent to the copper portion, and displacement plating surface portions of the copper portion with a plating metal more noble than copper and different than copper. The method including displacement plating provides selective and self-limiting thickness plating and enhances the electromigration resistance of the interconnect structure.
The displacement plating may include subjecting the copper portion to a plating bath including the plating metal. Because displacement plating is used and is not an electroless plating process, the concentration of the metal in the aqueous plating bath and the plating time are not critical.
The method may further include annealing the integrated circuit device after the displacement plating to diffuse the plating metal into the copper portion. For example, the displacement plating and annealing may form an electromigration resistant region having a thickness less than about 100 xc3x85.
The plating metal may comprise at least one of silver, gold, mercury, rhodium, palladium, iridium, and platinum. In some embodiments, the copper portion comprises an interconnect line, and the displacement plating is performed after forming the interconnect line and before forming the at least one barrier layer. In other embodiments, the copper portion comprises a copper seed layer formed on the at least one barrier layer, and displacement plating is performed after forming the seed layer on the at least one barrier layer. In other words, in these embodiments the plating layer is formed on an upper surface of the seed layer opposite the underlying barrier layer. Of course, in some embodiments, both techniques can be used.
In accordance with another aspect of the invention, the copper seed layer may be a doped copper seed layer including at least one of calcium, cadmium, zinc, neodymium, tellurium, and ytterbium. This may further improve or enhance the electromigration resistance.
The method may also include electroplating additional copper onto the displacement plated copper seed layer, such as to fill an opening in a dielectric layer and thereby provide a vertical interconnection or via for the device. In addition, the at least one barrier layer may comprise one of tantalum nitride and tantalum silicon nitride.